module ysyx_23060189_CLINT #
(
  parameter integer dataWidth = 32,
  parameter integer addrWidth = 32
)
(
  /* Slave <=> Slave interface */
  input  wire                 ACLK,
  input  wire                 ARESETn,

  input  wire                 ren,
  input  wire [addrWidth-1:0] raddr,
  output reg  [dataWidth-1:0] rdata,
  output reg                  rvalid,

  input  wire                 wen,
  input  wire [addrWidth-1:0] waddr,
  input  wire [dataWidth-1:0] wdata,
  input  wire [7:0]           wmask,
  output wire                 wdone
);
  // reg define
  reg [63:0] mtime;

  assign wdone = 0;

  // add one to the mtime register every cycle
  always @(posedge ACLK) begin
    if (ARESETn == 0) mtime <= 0;
    else mtime <= mtime + 1;
  end

  /* read mtime */
  // rdata
  always @(posedge ACLK) begin
    if (ARESETn == 0) rdata <= 0;
    else if (ren && raddr == 32'ha0000048) rdata <= mtime[31:0];
    else if (ren && raddr == 32'ha000004c) rdata <= mtime[63:32];
    else rdata <= 0;
  end
  // rvalid
  always @(posedge ACLK) begin
    if (ARESETn == 0) rvalid <= 1'b0;
    else if (ren) rvalid <= 1'b1;
    else rvalid <= 1'b0;
  end

endmodule
